1. Field of the Invention
The present invention relates to a semiconductor layout structure, and more particularly, to a semiconductor layout structure for static random access memory (hereinafter abbreviated as SRAM) cells.
2. Description of the Prior Art
In recent years, with widespread use of mobile terminal equipment, digital signal processing in which bulk data such as sounds or images is processed at high speed has been increasingly important. SRAM, which is capable of high-speed access processing, holds an important place as a semiconductor memory device to be mounted on such mobile terminal equipment.
Each of SRAM cells include a bistable circuit, which does not require refreshing. The switching speed of each bistable circuit is determined by the resistance and capacitance of the control electrodes of the transistors and the connection of the transistors within the circuit, thereby determining the slew rate of its output voltage. In addition to the desirability of forming larger numbers of SRAM cells and arrays on a chip of reasonable size, there is substantial incentive toward size reduction and integrated density increase in each cell.
SRAM memory cells and arrays are fabricated by forming metal contacts such as word line contacts, bit line contacts, VSS contacts and VCC contacts, etc., over transistors to electrically connect these SRAM memory cells and arrays together and ensure normal read and write operations. Word line contacts are electrically connected by higher interconnect layer(s) such as first metal (M1) layer of an interconnection structure; bit line contacts are electrically connected by higher interconnect layer(s) such as M1, first via (V1) layer and second metal layer (M2) of the interconnection structure.
In applying prior design layout rules, however, problems arose during the fabrication of high-density small-sized SRAM cell arrays: Due to pattern density effect, after patterning, the sizes of metal contact holes at or near a dummy edge cell are larger than the sizes of other metal contact holes within the dense area of a bit cell. Or, it is found that the end of the line patterns are spontaneously enlarged and such phenomenon is referred to line-end effect. What's more adverse is that optical proximity correction (hereinafter abbreviated as OPC) will even enlarge the sizes of these metal contact holes because they are near iso area (the area with relative lower pattern density). As a result, the enlarged contact will contact the dummy gate and thus electrical current may go short through the dummy gate. Such kind of undesirable electrical short is extremely damaging to the formed circuit devices.
Therefore, there is still a need for an improved design layout for the SRAM cell arrays.